1. Field of the Invention
The present invention relates to a decoding circuit, and more particularly to, a decoding circuit for a memory device, which is improved in an operation of chip so as to enable the operation to be predictable by making a decoded result corresponding to an undefined code become a specific value.
2. Description of the Related Art
Generally, a semiconductor memory device 10 (referring to FIG. 1D) such as SRAM, DRAM, and a Flash memory is comprised of a decoding circuit 12 which defines a control signal -for instance, CAS Latency (namely, CL) or Write recovery time (namely, tWR)- for setting an internal operation of the memory device 10 by receiving an address signal. For reference, CL denotes the minimum number of clocks from inputting a column address to outputting data and tWR denotes time from writing data in a cell to precharging the data.
For instance, the decoding circuit 12 as shown in FIG. 1D applied to CL combines an address signal applied through the fourth (A4), fifth (A5), and sixth (A6) address pins among address signals, and outputs signal corresponding to one of CL 2, 3, 4, 5, and 6. Furthermore, the decoding circuit 12 as shown in FIG. 1D applied to tWR combines an address signal applied through the ninth (A9), tenth (A10), and eleventh (A11) address pins among address signals, and outputs a signal corresponding to 2, 3, 4, 5, and 6.
Hereinafter, it will be described about the conventional decoding circuit with reference to FIGS. 1a, 1b, and 1c, and FIGS. 2a, 2b, and 2c. 
FIGS. 1a, 1b, and 1c are circuit diagrams illustrating a decoding circuit for a memory device 10 applied to the conventional CAS latency CL. FIG. 1a shows a definition (truth) table for CL, (wherein A4. A5. and A6 correspond to the respective fourth, fifth and sixth address pins, wherein the “Reserved” items indicated in FIG. 1a correspond to the unspecified address signals, and “2”, “3”, “4”, “5”, and “6” items Indicated in FIG. 1a correspond to the specified address signals), FIG. 1b shows a circuit for generating an address signal used in a semiconductor memory device by a control signal (Mode REGister set: MREG) (wherein A4. A5. and A6 correspond to the respective fourth, fifth and sixth address pins, and /A4, /A5, and /A6 correspond to the respective fourth, fifth and sixth complementary address pins), and FIG. 1c shows a decoding circuit for outputting CL (wherein A4, A5, and A6 correspond to the respective fourth, fifth and sixth address pins, and /A4. /A5, and /A6 correspond to the respective fourth, fifth and sixth complementary address pins) with a specific value by combining with an address signal generated from the circuit in FIG. 1b. 
For Example, if the specified address signals at the address pins A6, A5, A4 generated by control signals (MREG6, MREG5, MREG4 are (1, 0, 0) in sequence, then the value of the outputted control signal is a predetermined value corresponding to 4 clock periods of the CL as shown outputted. In FIG. 1a and in FIG. 1c as indicated by a “4”.
On the other hand, if the unspecified address signals at the address pins A6, A5, A4 generated by control signals MREG6, MREG5, MREG4 in FIG. 1b are (0, 0,0), (0, 0, 1), or(1, 1, 1), CL outputted from FIG. 1c is set in an undefined state (i.e., a reserved state) as shown in FIG. 1a. 
Therefore, if the address signal corresponding to the undefined CL is inputted, it can't be predicted for an output from the conventional decoding circuit. In response to this, it can't be checked for an operational condition of a memory device as well. Especially, a peak current may flow in the memory device.
Meanwhile, FIGS. 2a, 2b, and 2c are circuit diagrams illustrating a decoding circuit applied to the conventional tWR. FIG. 2a shows a definition table for tWR (wherein A9, A10, and A11 correspond to the respective ninth, tenth and eleventh address pins and /A9, /A10, and /A11 correspond to the respective ninth, tenth and eleventh complementary address pins, wherein the “Reserved” item in FIG. 2a correspond to the unspecified signals, and “2”, “3”, “4”, “5”, and “6” items in FIG. 2a correspond to the specified signals), FIG. 2b shows a circuit for generating an address signal (wherein A9, A10, and A11 correspond to the respective ninth, tenth and eleventh address pins and /A9, /A10, and /A11 correspond to the respective ninth, tenth and eleventh complementary address pins), used in a semiconductor memory device 10 by a control signal (Mode REGister set: MREG), and FIG. 2c shows a decoding circuit (wherein A9, A10, and A11 correspond to the respective ninth, tenth and eleventh address pins and /A9, /A10, and /A11 correspond to the respective ninth, tenth and eleventh complementary address pins) for outputting tWR with a specific value by combining the specified or unspecified address signal generated from the circuit in FIG. 2b. 
That is, if the specified address signals at address pins A11, A10, A9 generated by control signals MREG11, MREG10, MREG9 are (1, 0, 0) in sequence, then the value of the outputted control signal is a predetermined value corresponding to 5 clock periods for tWR as shown outputted in FIG. 2a and FIG. 2c as a “5”.
On the other hand, if the unspecified address signals delivered to the address pins A11, A10, A9 generated by control signals MREG11, MREG10, MREG9 are (0, 0, 0), (0, 0, 1) or (1, 1, 1), then the value of the outputted control signal is a reserved value directing the tWR in an undefined state (i.e., a reserved state) as shown in FIG. 2a. 
Accordingly, if the address signal corresponding to the undefined tWR is inputted, it can't be predicted for an output from the conventional decoding circuit. In response to this, it can't be checked for an operational state of a memory device as well. Especially, a peak current may flow in the memory device.
As aforementioned, in case that an address signal which is not defined for CL or tWR is generated, the conventional decoding circuit for a memory device causes a mis-operation in a memory device.